1. Field of the Invention
The present invention relates generally to semiconductor devices, more particularly to a method and system for controlling and maintaining an effective channel length in a semiconductor device by adjusting ion implant conditions derived from a fed-forward measurement of the gate electrode.
2. Description of Related Art
Over the years, in order to keep up with modern technology, it has been indispensably necessary to reduce semiconductor device size as well as enhance performance thereof. Semiconductors which have been decreased in size over the years have included, but are not limited to, field effect transistors (FETs), metal oxide semiconductor FETs (MOSFETs), complementary metal oxide silicon FETs (CMOS FETs), and the like. However, in decreasing feature sizes of the modern semiconductors, the bearable error of feature size control tolerances have also been reduced. As feature size control tolerances decrease, the ability to produce FETs with smaller specifications becomes increasing difficult, and as such, the normal random variances produced by such FETs provides undesirable semiconductor circuits.
In a conventional semiconductor, such as a FET, current flows along a semiconductor path called a channel. FIG. 1A illustrates a typical example of a CMOS device 20 comprising an NFET 1 and a PFET 2, while FIG. 1B illustrates the left half NFET 1 and the right half PFET 2 superimposed. As further illustrated, the conventional CMOS FET 20 has a gate electrode 3 having a gate width 21. The gate electrode may be offset by a variety of spacers, such as, spacers 4, 5, and 6, whereby the spacer 4 may define an ion implantation mask for creating a lightly doped drain (LDD) region 11, or an extension of the NFET 1, while spacer 5 may define an ion implantation mask for creating a LDD region 12 of the PFET 2. Spacer 6 may define an ion implant mask of both FETs for creating a source region 13 and drain region 14 of the substrate for both FETs. The gate electrode 3 lies over a thin gate insulator film 8, wherein the gate is positioned above and between shallow trench isolation regions 9 (xe2x80x9cSTIxe2x80x9d). Therebetween the shallow trench isolation regions 9 lies LDD regions 11 and 12, whereby the region of substrate located between LDD regions 11 and 12, under the gate electrode 3, constitutes the channel. As will be recognized, when the gate electrode 3 is turned xe2x80x9con,xe2x80x9d a depletion zone 17 forms in the channel whereby the region of substrate surface under the gate electrode 3, between edges of the depletion zone 17, is called an effective channel length 18 of the FET.
In a FET, any variation between a desired gate electrode width and the actual formed gate electrode width has a first-order effect on the effective channel length, while the effective channel length has a first-order effect on the drive current of the FET. Likewise, the drive current of the FET has a first-order effect on the speed of the resultant circuit having an effect on the maximum clocking frequency. As will be recognized, a circuit""s value, performance, and consumer desirability are typically determined by the maximum clocking frequency of the resultant circuit. Thus, the effective channel length of a FET affects the resultant circuit""s overall performance, value, and desirability. Therefore, as feature sizes of the modern semiconductors continue to decrease, and therewith the control of the tolerable feature error, any variation between a desired gate electrode width and the actual, as-formed gate electrode affects the underlying effective channel length, thus affecting the clocking frequency to provide a circuit having decreased value and desirability.
Therefore, a need exists in the art to control the effective channel length to provide a manufacturing process that provides FETs, and thus circuits, to meet desired specifications. Prior art is aimed at controlling the effective channel length using Rapid Thermal Anneal (RTA) or drive-in process steps, whereby any variation of the actual gate electrode from the ideal gate electrode may be corrected by adjusting RTA time or temperature using a downstream process. However, adjusting RTA time or temperature using downstream processes can be problematic with other device parameters including overlap capacitance, increasing the thermal budget, and affecting both NFET and PFET as well as all dopant simultaneously, for example. As a result of modern semiconductors having smaller effective channel lengths, and thus being at an increased sensitivity to overlap capacitance due to the associated reduced tolerable feature error and thermal cycle budget, adjusting RTA time or temperature using downstream processes is not ideal for controlling a smaller effective channel length in modern semiconductors.
Prior art is also directed to controlling the effective channel length by correcting for variations in the gate electrode using techniques such as photolithography, polysilicon reactive ion etching (xe2x80x9cRIExe2x80x9d), and the possible use of hardmasks for gate definition. For example, prior art is directed to techniques of controlling gate width variations by photolithography to reactive ion etching xe2x80x9cRIExe2x80x9d whereby a measurement of the photoresist mask width determines an adjustment to the RIE etch-bias to control the gate width. However, as gate width dimensions continue to shrink to sub-quarter micron in modern semiconductors all available etch-bias may be used in achieving such sub-lithographic dimensions, thereby leaving no available etch-bias for later adjustments to control the smaller effective channel lengths in modern semiconductors.
Thus, as the gate electrodes of modern semiconductors continue to shrink to sub-quarter micron, typically less than 0.25 xcexcm, it is becoming more difficult to effectively and efficiently control the associated smaller effective channel lengths, and thus more difficult to provide fast, reliable, and desirable semiconductors. Therefore, a need continues to exist in the art to provide improved systems and methods of forming, controlling and maintaining smaller effective channel lengths in modern semiconductors.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide an improved system and method of forming and controlling an effective channel length in a semiconductor.
Another object of the present invention is to provide an improved system and method for compensating for gate electrode width deviation from target.
It is another object of the present invention to provide a system and method for controlling channel length or other device parameter by compensating for gate electrode width deviation from target.
Yet another object of the present invention is to provide an improved semiconductor, such as a FET, having a gate width less than about 0.251 xcexcm which exhibits improved yield and performance.
It is another object of the present invention to provide a more reliable, efficient, effective, and desirable FET.
Still another object of the present invention is to provide a manufacturing process that decreases variance of one or more device parameters while simultaneously increasing product yield thus decreasing scrap.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a method and system of forming a semiconductor device, such as a FET, MOSFET, and CMOS, whereby a gate electrode is provided over a substrate and subsequently a dimension of the gate electrode is determined. The determined dimension of the gate electrode is then fed forwarded to a feed-forward controller wherein an ion implant recipe, including ion implant recipe comprising n-type and p-type impurities, is determined based on the gate electrode dimension, which when implanted into the substrate defines the doped regions of the substrate while simultaneously controlling the correlating semiconductor parameters of the substrate.
Preferably, the gate electrode may include polysilicon, antimony, arsenic, boron, carbon, germanium, selenium, sulfur, tellurium, gallium arsenide, and indium antimonide. The dimension of the final gate electrode is determined whereby such dimensions preferably include gate electrode width, gate electrode height, gate electrode length, gate electrode sheet resistance, gate electrode sidewall profile, and mixtures thereof. The ion implant recipe is in the feed forward controller based on the fed-forward gate electrode dimension. The determined ion implant recipe is then implanted into the substrate to define the doped regions of the substrate, preferably the halo, lightly doped drain (LDD) extensions, source and drain regions, and mixtures thereof, while simultaneously controlling correlating semiconductor parameters of the substrate including the effective channel length, overlap capacitance, cut off frequency, switching time, and mixtures thereof.
The present invention compensates for both gate electrode dimensions which are larger than a desired gate electrode dimension, as well as gate electrode dimensions which are smaller than a desired gate electrode dimension. Furthermore, both the larger and smaller gate electrodes are compensated for in a single ion implantation process based on a single measurement of the gate electrode.
In the present invention, the step of determining the ion implant recipe may comprise comparing the determined dimension of the gate electrode with a desired dimension of the gate electrode within the feed-forward controller. An ion implant condition adjustment of an ideal ion implant recipe is then determined based on any difference between the determined dimension of the gate electrode and the desired dimension. Subsequently, the ion implant recipe is determined base on the ion implant condition adjustment of the ideal ion implant recipe within the feed-forward controller. In the present invention, the ion implant condition adjustment of the ideal ion implant recipe may be determined using Response Surface Methodology (RSM) or Design Of Experiments (DOE) model.
In an embodiment of the present invention, the ion implant recipe may be selected from a set of pre-qualified ion implant recipes from within the feed-forward controller, whereby the selected ion implant recipe compensates for any perceived deviation in the determined dimension of the gate electrode from a targeted dimension of the gate electrode.
Alternatively, the ion implant recipe determined within the feed-forward controller may be a unique ion implant recipe which when implanted into the substrate compensates for any perceived deviation in the determined dimension of the gate electrode from a targeted dimension of the gate electrode. In the embodiment where the ion implant recipe comprises a unique ion implant recipe, the unique ion implant recipe is determined using a model of the semiconductor parameters based on the implantation of a nominal ion implant recipe and any calculated deviation between the determined gate electrode dimension and the targeted dimension of the gate electrode.
In the present invention, the feed-forward controller may further include a detuning means selected from the group consisting of filtering, estimation, and smoothing algorithms. Such detuning means prevents the feed-forward controller from reacting to measurement noise.
Furthermore, in the present invention, the semiconductor parameters of an NFET and a PFET may be formed and controlled simultaneously by a single step of implanting the determined ion implant recipe derived from the single gate electrode dimension. Such semiconductor parameters of the NFET and the PFET may be adjusted by differing ion implant dosages and energies based only on such single step of implanting the determined ion implant recipe derived from the single gate electrode dimension.
In a preferred embodiment, a gate electrode width is determined and forwarded to the feed-forward controller for determining the ion implant recipe based on the gate electrode width which is then implanted into the substrate to define the doped regions of the substrate while simultaneously controlling an effective channel length of the semiconductor. A lightly doped region or Halo region may be implanted into the substrate prior to doping the portion of the substrate using the adjusted ion implant recipe. In such an embodiment, the gate electrode width is determined using a mechanical measuring technique selected from the group consisting of scanning electron microscopy, reflectance measurements, atomic form microscopy, image shearing, and mechanical measurement. Alternatively, the gate electrode width may be determined using a non-mechanical measuring technique selected from the group consisting of estimation, inference, and assumption based on predetermined gate electrode width of a second, similar gate electrode.